AMD Ryzen Memory
Sub-Timings & FCLK Tuner
in Réunion
Calculate Fabric Clock (FCLK), UCLK ratios, and primary DDR5 CAS latency sub-timings for your Ryzen 7000 / 9000 series processor based on your IC manufacturer die.
Configuration Input
Recommended Configuration
Hynix M-Die
GoodExcellent sweet spot for 6000-7200 MT/s Ryzen 7000 builds.
Primary Timing Recommendations for 6,000 MT/s
| Parameter | Symbol | Value | Description |
|---|---|---|---|
| CAS Latency | CL | 30 | Columns Address Strobe – cycles from READ command to data |
| RAS to CAS Delay | tRCD | 30 | Row → Column activation delay in cycles |
| Row Precharge | tRP | 30 | Duration to close a DRAM row to free bank |
| Row Active Time | tRAS | 62 | Minimum active time before precharge is issued |
| Fabric Clock | FCLK | 3000 MHz | AMD Infinity Fabric interconnect frequency |
| Memory Clock | MCLK | 3000 MHz | Physical DDR5 memory controller frequency |
DDR5 Speed Tier Comparison — Hynix M-Die
BIOS Setup Guide — Ryzen 7000 / 9000 DDR5 Memory OC
Start by loading the manufacturer EXPO (AMD) or XMP 3.0 (Intel) profile in BIOS. This sets the base validated timings.
Set FCLK to 3000 MHz to match your memory frequency. Avoid Auto — it often sets 1:2 ratio unnecessarily.
At speeds above 4000 MT/s FCLK, the controller will drop to 2:1 ratio. Set UCLK = MCLK/2 for stability.
Set CL30-30-30-62. Start with these, then tighten secondary timings like tRFC if stable.
Run TestMem5 MemTest86 or Karhu RAM Test for 2+ hours. Any errors require loosening CL or raising DRAM voltage slightly.
For Samsung B-Die, 1.35–1.4V VDDQ is typically safe. Hynix M-Die performs well at 1.35V. Never exceed 1.5V without custom cooling.
Why AMD Ryzen DDR5 Memory Tuning Matters
AMD's Zen 4 and Zen 5 architectures use an internal Infinity Fabric (IF) bus that directly links the CPU cores to the memory controller. The FCLK (Fabric Clock) must divide evenly into the memory clock (MCLK) — running them at a 1:1 ratio yields the absolute lowest memory access latency and highest bandwidth. For Ryzen 7000 / 9000 platforms running DDR5, the sweet spot is 6000 MT/s, where FCLK runs at 2000 MHz in 1:1 sync with MCLK at 3000 MHz.
The IC (Integrated Circuit) die manufacturer determines the physical limits of overclocking. Samsung B-Die is the gold standard — it scales aggressively past 7200 MT/s with tight CAS timings. Hynix M-Die dominates the midrange, and Micron die chips prioritize stock reliability over headroom. Selecting the wrong voltage or timing for a given die can cause memory training failures, blue screens, or random crashes under load.
The true memory latency in nanoseconds is computed as (CL ÷ (speed/2000)) × 1000. So a DDR5-6000 CL30 kit has 10.0 ns latency, while DDR5-7200 CL36 still achieves 10.0 ns — meaning faster kits are only beneficial if they also tighten the primary timings proportionally.